1. Technical Field
The present invention generally relates to diagnosing a circuit, and more particularly, to systems and methods for locating defective components within a circuit.
2. Description of the Related Art
Aggressive scaling of complementary metal-oxide-semiconductor (CMOS) technology has significantly improved performance and reduced the manufacturing cost of chips. However, despite these improvements, increased scaling may detrimentally affect chip reliability due to elevated chip temperature resulting from increased power density and leakage current. In addition, scaling has a significant impact on hard fault rates. Leakage current stemming from scaling reduces the reliability of traditional reliability circuit screening methods such as burn-in and IDD, testing. Currently, large chips have more than a million gates. As such, screening all defective chips is extremely difficult and expensive for large chips. For example, even if a screening scheme achieves 99% stuck-at fault coverage for a million gate chip, 20,000 stuck-at faults remain uncovered. With regard to deep submicron technology, there are many defects that cannot be detected with existing fault models.
Furthermore, even if a test technique is able to screen and detect 100% of defective chips, working chips may become defective before their expected life spans as a result of power surge, human mistakes, and other factors. Since built-in self-repair (BISR) was first developed for standard DRAM devices to improve yield, BISR has been widely applied in a variety of other memory products. Currently, repair using BISR are done during manufacturing of circuits rather than in the field.
Existing techniques for locating defects in CMOS circuits employs compressed signatures that are indications of chip responses to test patterns. These techniques identify a set of candidate defect sites from the signatures by using extensive computations and, as a result, require an on-chip or off-chip processor. Although redundancy-based fault tolerance techniques have been used in systems that require high reliability, these techniques are less attractive solutions mainly due to the increase in power consumption resulting from their use.
Other techniques include self-diagnosis schemes that use special on-board hardware to locate defective chips on a board. Responses of each chip are sequentially collected by a space/time-compression circuit through a bus, one at a time. Thus, if the board includes many chips, a long diagnosis time is required. After responses from all chips are compressed into a signature, the signature is compared with a fault free signature and defective chips are identified using a decoder. The on-broad self-diagnosis circuit, which is usually based on a Reed-Solomon code, can locate a pre-determined number of defective chips.
However, existing techniques fail to identify defective blocks that have varying sizes within a chip. Furthermore, existing techniques fail to provide a means for processing a large number of responses in parallel with low hardware complexity.